This course covers the fundamental issues of designing a digital system. We will begin by introducing number systems, Boolean algebra, and logic gates. After that, we will discuss the minimization techniques of Boolean functions using Karnaugh Map as well as algorithmic procedures. In the second half, we will focus on the design techniques for combinational, sequential, and memory circuits. Finally, we will introduce the more modern design concept using Register-Transfer-Level (RTL) descriptions. Upon the completion, the students will know how to realize a given digital system, e.g., the arithmetic logic unit (ALU) of a CPU, into a logic circuit.This course covers the fundamental issues of designing a digital system. We will begin by introducing number systems, Boolean algebra, and logic gates. After that, we will discuss the minimization techniques of Boolean functions using Karnaugh Map as well as algorithmic procedures. In the second half, we will focus on the design techniques for combinational, sequential, and memory circuits. Finally, we will introduce the more modern design concept using Register-Transfer-Level (RTL) descriptions. Upon the completion, the students will know how to realize a given digital system, e.g., the arithmetic logic unit (ALU) of a CPU, into a logic circuit.
本課程旨在介紹基本數位邏輯設計，其中包含邏輯設計的理論、原理、元件、電路及其應用等。
This course aims to introduce basic digital logic design, including the theory, principles, components, circuits and applications of logic design.
M. Morris Mano and Michael D. Ciletti, DIGITAL DESIGN 5th edition, Pearson Prentice Hall
M. Morris manoh and Michael D. Ci Le group, digital design 5TH edition, Pearson Prentice hall
| 評分項目 Grading Method | 配分比例 Grading percentage | 說明 Description |
|---|---|---|
| 小考(quiz)、作業報告(Homeworks)小考(quiz)、作業報告(Homeworks) Quiz, Homeworks |
35 | |
| 期中考(Midterm Exams)期中考(Midterm Exams) Midterm Exams |
25 | |
| 期末考(Midterm Exams)期末考(Midterm Exams) Midterm Exams |
30 | |
| 出席率(attendence)出席率(attendence) attendance |
10 |
