本課程旨在深入探討後摩爾時代下，積體電路產業如何透過「小晶片」設計方法與「異質整合」先進構裝技術，持續推動系統效能提升、功耗降低與多功能融合。課程內容涵蓋從基礎概念、關鍵製程技術（如2.5D/3D IC、中介層、混合鍵合）、設計挑戰（熱管理、信號完整性、測試策略），到最新應用案例與未來發展趨勢。學生將能全面理解從單一晶片到系統級整合的技術演進、挑戰與解決方案。

This course aims to deeply explore how the integrated circuit industry continues to promote system performance improvement, power consumption reduction and multi-functional integration in the post-Moore era through "small chip" design methods and "heterogeneous integration" advanced construction technologies. The course content covers basic concepts, key process technologies (such as 2.5D/3D IC, interposer, hybrid bonding), design challenges (thermal management, signal integrity, test strategies), to the latest application cases and future development trends. Students will gain a comprehensive understanding of technology evolution, challenges and solutions from single chip to system-level integration.

探討小晶片異質整合與先進構裝技術如何突破傳統摩爾定律的極限。課程內容首先介紹半導體封裝的演進趨勢，並定義小晶片 (Chiplet) 設計架構與異質整合 (Heterogeneous Integration) 的核心概念。課程內容首先探討先進封裝材料科學，包括基板、中介層與微凸塊技術的選擇與特性。課程將重點講解2.5D/3D封裝的關鍵技術，如矽穿孔 (TSV) 與混合鍵合 (Hybrid Bonding)，並分析中介層設計對信號完整性的影響。此外，課程亦涵蓋熱管理技術、扇出型封裝，以及光子晶片整合與光電共封裝等前瞻技術。本課程的目標為使學生具備獨立分析與解決製程問題的能力，為未來從事半導體產業研發或製程工程等相關職務奠定堅實的基礎。

Explore how small chip heterogeneous integration and advanced construction technology can break the limits of traditional Moore's Law. The course content first introduces the evolution trend of semiconductor packaging and defines the core concepts of chiplet design architecture and heterogeneous integration. The course content begins with an exploration of advanced packaging materials science, including the selection and characterization of substrate, interposer and micro-bumping technologies. The course will focus on key technologies of 2.5D/3D packaging, such as through-silicon via (TSV) and hybrid bonding (Hybrid Bonding), and analyze the impact of interposer design on signal integrity. In addition, the course also covers thermal management technology, fan-out packaging, as well as forward-looking technologies such as photonic chip integration and optoelectronic co-packaging. The goal of this course is to equip students with the ability to independently analyze and solve process problems, laying a solid foundation for future careers in semiconductor industry R&D or process engineering and other related positions.

1.曲建仲，晶圓代工與先進封裝產業科技實務(第二版)，全華圖書。
2.陳信文、陳立軒、林永森、陳志銘，電子構裝技術與材料(2版)，高立圖書。
3.鍾文仁、陳佑任，IC封裝製程與CAE應用(第四版)，全華圖書。

1. Qu Jianzhong, Technology Practice in Wafer Foundry and Advanced Packaging Industry (Second Edition), Quanhua Books.
2. Chen Xinwen, Chen Lixuan, Lin Yongsen, Chen Zhiming, Electronic Assembly Technology and Materials (2nd Edition), Gao Li Books.
3. Zhong Wenren, Chen Youren, IC packaging process and CAE application (4th edition), Quanhua Books.