1. Understanding basic Verilog topics: gate-level modeling,data flow modeling and behavioral modeling.
2. Studying advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, logic synthesis, and advanced verification techniques.
3. Use Verilog HDL to design and simulate digital systems.1. Understanding basic Verilog topics: gate-level modeling, data flow modeling and behavioral modeling.
2. Studying advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, logic synthesis, and advanced verification techniques.
3. Use Verilog HDL to design and simulate digital systems.
1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog 硬體描述語言 (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), 黃英叡、黃稚存, 全華, 2005
1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog Hardware Description Language (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), Huang Yingrui, Huang Zhicun, Quanhua, 2005
| 評分項目 Grading Method | 配分比例 Grading percentage | 說明 Description |
|---|---|---|
| 小考小考 Quiz |
25 | |
| Midterm examsMidterm exams midterm exams |
25 | |
| Final examFinal exam final exam |
25 | |
| homework and participationhomework and participation homework and participation |
15 | |
| 補救教學(彈性學習週)補救教學(彈性學習週) Remedial Teaching (Flexible Learning Week) |
10 |
