1016 - 硬體描述語言

Hardware Description Language

教育目標 Course Target

1. Understanding basic Verilog topics: gate-level modeling,data flow modeling and behavioral modeling.
2. Studying advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, logic synthesis, and advanced verification techniques.
3. Use Verilog HDL to design and simulate digital systems.

1. Understanding basic Verilog topics: gate-level modeling,data flow modeling and behavioral modeling.
2. Studying advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, logic synchronization, and advanced verification techniques.
3. Use Verilog HDL to design and simulate digital systems.

參考書目 Reference Books

1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog 硬體描述語言 (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), 黃英叡、黃稚存, 全華, 2005

1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog Hardware Description Language (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), Huang Ying, Huang Zhicun, Quanhua, 2005

評分方式 Grading

評分項目
Grading Method		 配分比例
Percentage		 說明
Description
小考
Small exam
 25
Midterm exams
Midterm exams
 25
Final exam
Final exam
 25
homework and participation
homework and participation
 15
補救教學(彈性學習週)
Rescue Teaching (Elastic Learning Week)
 10

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課程資訊 Course Information

基本資料 Basic Information
  • 課程代碼 Course Code: 1016
  • 學分 Credit: 3-0
  • 上課時間 Course Time:
    Friday/6,7,8[ST436]
  • 授課教師 Teacher:
    劉榮春
  • 修課班級 Class:
    資工系2-4
  • 選課備註 Memo:
    資電工程學群課程
選課狀態 Enrollment Status
目前選課人數 Current Enrollment: 46 人
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